The present invention relates to a semiconductor structure and method of manufacture, and more particularly to a semiconductor device and manufacturing method thereof.
With the continuous decrease of semiconductor feature sizes, capacitive crosstalk between metal interconnect layers has a significant impact on semiconductor device performance. The use of a porous low-k dielectric layer disposed between metal interconnect layers is a good way to solve the problem of capacitive crosstalk.
The number of metal interconnect layers in a logic circuit of a semiconductor device may range from a few to more than 10 layers, each of the metal interconnect layers forms a respective layer of a metal interconnect structure. Referring to FIG. 1A, a front-end device may have an etch stop layer 101 disposed on a semiconductor substrate 100 and a porous low-k dielectric layer 102 disposed on etch stop layer 101, a metal interconnect structure 103 is formed by dry etching in porous dielectric layer 102. Metal interconnect structure 103 includes a through-hole 103a and a trench 103b. Referring to FIG. 1B, a diffusion barrier layer 104 is formed by a physical vapor deposition process on sidewalls and bottoms of metal interconnect structure 103. Diffusion barrier layer 104 comprises Ta/TaN. Then, a copper seed layer and a copper interconnect layer are sequentially formed. However, in the conventional process, the interface surface between the porous low-k dielectric layer and the diffusion barrier layer is rough, leading to poor adhesion between the porous low-k dielectric layer and the diffusion barrier layer, thereby reducing yield and electrical interconnect performance of the semiconductor device.
For these and other reasons there is a need for the present invention.